View LPC2365FBD100_2838097.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

es_lpc2365 errata sheet lpc2365 rev. 6 ? 20 april 2011 errata sheet document information info content keywords lpc2365 errata abstract this errata sheet describes both the known functional problems and any deviations from the electrical specific ations known at t he release date of this document. each deviation is assigned a number and its history is tracked in a table at the end of the document.
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 2 of 12 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors es_lpc2365 errata sheet lpc2365 revision history rev date description 6 20110420 ? added note.2. 5 20110301 ? added adc.1. 4 20100401 ? the format of this errata sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? added ethernet.1 3 20100122 ? added vbat.2 2 20090511 ? added rev d 1 20080904 ? first version
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 3 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 1. product identification the lpc2365 devices typically have the following top-side marking: lpc2365xxx xxxxxxx xxyywwr[x] the last/second to last letter in the third line (field ?r?) will identify the device revision. this errata sheet covers the following revisions of the lpc2365: field ?yy? states the year the device was manufactured. field ?ww? states the week the device was manufactured during that year. 2. errata overview table 1. device revision table revision identifier (r) revision description ?a? second device revision ?b? third device revision ?d? fourth device revision table 2. functional problems table functional problems short description revision identifier detailed description ethernet.1 ethernet txconsumein dex register does not update correctly after the first frame is sent ?a?, ?b?, ?d? section 3.1 on page 5 core.1 incorrect update of the abort link register in thumb state ?a?, ?b?, ?d? section 3.2 on page 5 flash.1 operating speed out of on-chip flash is restricted ?a? section 3.3 on page 6 mam.1 code execution failure ca n occur with mam mode 2 ?a? section 3.4 on page 7 deep power-down.1 deep power-down mode is not functional ?a?, ?b? section 3.5 on page 7 vbat.1 increased power consumption on vbat when vbat is powered before the 3.3 v supply used by rest of device ?a?, ?b? section 3.6 on page 7 vbat.2 the vbat pin cannot be left floating ?a?, ?b? section 3.7 on page 8 adc.1 external sync inputs not operational ?a?, ?b?, ?d? section 3.8 on page 9 table 3. ac/dc deviations table ac/dc deviations short description revision identifier detailed description n/a n/a n/a n/a
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 4 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 table 4. errata notes table errata notes short description revision identifier detailed description note.1 when the input voltage is vi ? v dd i/o + 0.5 v on each of the following port pins p0.23, p0.24. p0.25, p0.26, p1.30, and p1.31 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. ?a?, ?b?, ?d? section 5.1 on page 10 note.2 on the lpc2365 rev d, design changes to the memory accelerator module were made to enhance timing and general performance. ?d? section 5.2 on page 10
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 5 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 3. functional problems detail 3.1 ethernet.1: ethernet txconsum eindex register does not update correctly after the first frame is sent introduction: the transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. af ter a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of txdescriptornumber has been reached. if the txconsumeindex equa ls txproduceindex the descriptor array is empty and the transmit channel will stop tr ansmitting until software produces new descriptors. problem: the txconsumeindex register is not updated correc tly (from 0 to 1) after the first frame is sent. after the next frame sent, the txconsumei ndex register is updated by two (from 0 to 2). this only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of txdesc riptornumber has been reached) work-around: software can correct this situation in many ways; for example, sending a dummy frame after initialization. 3.2 core.1: incorrect update of the abort link register in thumb state introduction: if the processor is in thumb state and executing the code sequence str, stmia or push followed by a pc relative load, and the str, stmia or push is aborted, the pc is saved to the abort link register. problem: in this situation the pc is saved to the abor t link register in word resolution, instead of half-word resolution. conditions: the processor must be in thumb state, and the following sequence must occur: <---- data abort on this instruction ldr rn, [pc,#offset] in this case the pc is save d to the link register r14_abt in only word resolution, not half-word resolution. the effect is that the lin k register holds an address that could be #2 less than it should be, so any abort handler co uld return to one instruction earlier than intended.
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 6 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 work-around: in a system that does not use thum b state, there w ill be no problem. in a system that uses thumb state but does not use data aborts, or does not try to use data aborts in a recoverable manner, there w ill be no problem. otherwise the workaround is to ensure that a str, stmia or push cannot precede a pc-relative load. one method for this is to add a nop before any pc-relative load instruction. however this is would have to be done manually. 3.3 flash.1: operating speed out of on-chip flash is restricted introduction: the operating speed of this device out of internal flash/sram is specified at 72 mhz. problem: code execution from internal flash is rest ricted depending upon the device revision: 1. rev ?a? devices: code execution from intern al flash is restricted to a maximum of 60 mhz. for example, use a pll output frequency of f cco = 360 mhz and divide it by 6 (cclksel = 5) to generate 60 mhz cpu clo ck (do not use even values for cclksel). considering the example (input crystal-12 mhz, n = 1, m = 12): f cco = 288 mhz the cpu clock configuration register (located at 0xe01f c104) can then be used to divide this frequency by 6 (cclksel = 5) to achieve 48 mhz. since this register only accepts odd values for cclksel, a division by 5 (cclksel = 4) is not a valid option. in both the above revisions, code can still execute out of sram at up to 72 mhz. work-around: none.
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 7 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 3.4 mam.1: under certain conditions in mam mode 2 code execution out of internal flash can fail introduction: the mam block maximizes the performance of the arm processor when it is running code in flash memory. it includes three 128-bit buffers called the prefetch buffer, the branch trail buffer and the data buffer. it can operate in 3 modes; mode 0 (mam off), mode 1 (mam partially enabled) and mode 2 (mam fully enabled). problem: under certain conditions when the mam is fully enabled (mode 2) code execution from internal flash can fail. the conditions under which the problem can occur is dependent on the code itself along with its positioning within the flash memory. work-around: if the above problem is encountered then mode 2 should not be used. instead, partially enable the mam using mode 1. 3.5 deep power-down.1: deep pow er-down mode is not functional introduction: deep power-down mode is like power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. this produces the lowest possible power consumption without actually removing power from the entire chip. problem: the power consumption in deep power-down mode does not meet the specifications. work-around: none. 3.6 vbat.1: increased power cons umption on vbat when vbat is powered before the 3.3 v supply used by rest of the device introduction: the device has a vbat pin which provides power only to the rtc and battery ram. vbat can be connected to a battery or the same 3.3 v supply used by rest of the device (v dd(3v3) pin, v dd(dcdc)(3v3) pin). problem: if vbat is powered before the 3.3 v supply, vba t is unable to source the start-up current required for the battery ram. therefore, power consumpt ion on the vbat pin will be high and will remain high until 3.3 v supply is pow ered up. once 3.3 v su pply is powered up, power consumption on the vbat pin will reduce to normal and subsequent power cycle on the 3.3 v supply will not cause an increased power consumption on the vbat pin. work-around: provide 3.3 v supply used by rest of the device first and then provide vbat voltage.
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 8 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 3.7 vbat.2: the vbat pin cannot be left floating introduction: the device has a vbat pin which provides powe r only to the real time clock (rtc) and battery ram. vbat can be connected to a batter y or the same supply used by rest of the device (v dd(3v3) pin, v dd(dcdc)(3v3) pin). the input voltage range on the vbat pin is 2.0 v minimum to 3.6 v maximum for temperature ? 40 ? c to +85 ? c. normally, if the rtc and the battery ram are not used, the vbat pin can be left floating. problem: if the vbat pin is left floating, the internal reset signal within the rtc domain may get corrupted and as a result, prevents the device from starting-up. work-around: the vbat should be connected to a battery or th e same supply used by rest of the device (v dd(3v3) pin, v dd(dcdc)(3v3) pin).
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 9 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 3.8 adc.1: external syn c inputs not operational introduction: in software-controlled mode (burst bit is 0) , the 10-bit adc can start conversion by using the following options in the a/d control register: problem: the external start conversion feature, ad0cr: start = 0x2 or 0x3, may not work reliably and adc external trigger edges on p2.10 or p1.27 may be missed. the occurrence of this problem is peripheral clock (pclk) depend ent. the probability of error (missing a adc trigger from gpio) is estimated as follows: ? for pclk_adc = 72 mhz, pr obability error = 12 % ? for pclk_adc = 50 mhz, probability error = 6 % ? for pclk_adc = 12 mhz, probability error = 1.5 % the probability of error is not affected by the frequency of adc start conversion edges. work-around: in software-controlled mode (burst bit is 0), the start conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. the user can also start a conversion by connecting an external trigger signal to a capture input pin (capx) from a timer peripheral to generate an interrupt. the ti mer interrupt routine can then start the adc conversion by setting the start bits (26:24) to 0x1. the trigger can also be generated from a timer match register. fig 1. a/d control register options
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 10 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 4. ac/dc deviations detail 4.1 n/a 5. errata notes detail 5.1 note.1 on each of the following port pins p0.23, p0 .24, p0.25, p0.26, p1 .30, and p1.31 (when configured as general purpose input pin (s)) , leakage current increases when the input voltage is vi ? v dd i/o + 0.5 v. care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 note.2 on the lpc2365 rev d, design changes to the memory accelerator module were made to enhance timing and general performance. design changes are intended to enhance performance in general and will result in minor difference s in the code execution timing between the previous device revisions and rev d. actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev d. this might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay.
es_lpc2365 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 6 ? 20 april 2011 11 of 12 nxp semiconductors es_lpc2365 errata sheet lpc2365 6. legal information 6.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 6.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 6.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners.
nxp semiconductors es_lpc2365 errata sheet lpc2365 ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 20 april 2011 document identifier: es_lpc2365 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 7. contents 1 product identification . . . . . . . . . . . . . . . . . . . . 3 2 errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 functional problems detail . . . . . . . . . . . . . . . . 5 3.1 ethernet.1: et hernet txconsumeindex register does not update correctly after the first frame is sent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 core.1: incorrect update of the abort link register in thumb state . . . . . . . . . . . . . . . . . . . . . . . . . 5 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 conditions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.3 flash.1: operating spee d out of on-chip flash is restricted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.4 mam.1: under certain conditions in mam mode 2 code execution out of intern al flash can fail . . . 7 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.5 deep power-down.1: deep power-down mode is not functional . . . . . . . . . . . . . . . . . . . . . . . . . . 7 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.6 vbat.1: increased power consumption on vbat when vbat is powered before the 3.3 v supply used by rest of the device. . . . . . . . . . . . . . . . . 7 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.7 vbat.2: the vbat pin cannot be left floating. . 8 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.8 adc.1: external sync i nputs not operational . . 9 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4 ac/dc deviations detail . . . . . . . . . . . . . . . . . 10 4.1 n/a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 errata notes detail . . . . . . . . . . . . . . . . . . . . . . 10 5.1 note.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 note.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 legal information . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

▲Up To Search▲

Price & Availability of LPC2365FBD100

	To Download LPC2365FBD100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .